The present invention relates generally to a method of replacing failed memory cells in a semiconductor memory device, and, more particularly, to a method for relieving failed memory cells by using redundant memory cells.
To decrease the size of computer systems, a large capacity memory is designed such that a plurality of functional block circuits, like a CPU, are integrated on the same LSI chip. Redundant memory cells are provided to relieve a memory cell when it fails. As shown in FIG. 1, a memory cell array 1 includes a plurality of bit lines BL and a plurality of word lines WL with memory cells C located at the individual intersections of the bit lines BL and the word lines WL. The memory cell array 1 further includes a redundant word line RW, a redundant bit line RB and a plurality of redundant memory cells RC. The redundant memory cells RC are located respectively at the intersections of the redundant word line RW and the individual bit lines BL, at the intersections of the redundant bit line RB and the individual word lines WL, and at the intersection of the redundant word line RW and the redundant bit line RB. A redundant cell row is formed along the redundant word line RW, and a redundant cell column is formed along the redundant bit line RB. The word lines WL, the redundant word line RW, the bit lines BL and the redundant bit line RB are connected via fuses H to a memory decoder 2.
When a memory cell CS at the second row and the first column fails, for example, the bit line BL or the word line WL which is associated with the failed memory cell CS is disconnected from the memory decoder 2. Then, a redundant memory cell in the redundant cell row or the redundant cell column is used in place of the failed memory cell. The location of the failed memory cell CS is specified in the first test based on the result of which decode line is physically switched. The switching is accomplished by the disconnection of the decode line by the fusion of the associated fuse H and a programming-based registration of the address of the failed memory cell CS. Next, a second test checks if switching of the failed memory cell to a redundant memory cell in the redundant cell row or the redundant cell column has been carried out properly. That is, second test checks that the disconnection of the decode line and the registration of the failure address have been correctly implemented.
The operation of functional block circuits on an LSI chip where a plurality of functional block circuits and a memory coexist is tested with a logic tester, while the operation of the memory is tested with a memory tester. Alternatively, the operations of both the functional block circuits and the memory are tested using the logic tester. An increase in the memory capacity leads to a longer time for testing an LSI. Since the switching from a failed memory cell to a redundant memory cell requires two tests and a physical switching task, the test time is further increased.